FIG. 1 shows a block diagram of a prior art information processing system 10 such as a computer system. Information processing system 10 is shown to comprise a central processing unit (CPU) 20, a host controller 40, a system memory 30, a graphics controller 70, a frame buffer 80, and a display unit 60. Display unit 60 can be a flat-panel LCD display or a CRT display or any other type that allows the graphics controller 70 to display information. Host controller 40 controls accesses to a system memory bus 78. Frame buffer 80 is generally implemented as a separate memory unit from the system memory 30.
In operation, CPU 20 generally sends display data to the graphics controller 70, which in turn, writes that display data into the frame buffer 80. It will be appreciated that the display data can be any graphics data or text. Some of the display data can be written from a source other than CPU 20. Graphics controller 70 periodically refreshes a screen on display unit 60 using the display data stored in frame buffer 80.
FIG. 2 shows a block diagram of another prior art information processing system 100. This information processing system 100 differs from the information processing system 10 in that the frame buffer is implemented along with the system memory in a single memory unit 130. Such a single memory unit has been implemented typically in order to take advantage of the increasingly higher capacity DRAM memories available and to reduce the number of components, thereby decreasing the cost of the overall information processing system 100.
The prior art graphics controllers may also include a CRT FIFO 190 (conceptual model shown in FIG. 3) for reading ahead display data from frame buffer 130, and displaying that display data on the display unit 160. The display data may be transformed into analog RGB signals using a digital to analog conveyer.
Graphics controller 170 generally waits until the display data in CRT FIFO 190 falls below a certain threshold (shown as low level water mark), and then reads the next piece of display data from system memory/frame buffer 130. In other words, graphics controller 170 reads next piece of display data when the data stored in CRT FIFO 190 falls below a predetermined threshold level.
In order to read the display data from frame buffer 130, graphics controller 170 asserts a memory request (MREQ) signal line. In response, host controller 140 grants access to system memory bus 173 by asserting a memory grant (MGNT) signal line. The graphics controller 170 then reads a burst of bytes that corresponds to next piece of display data to be displayed. This display data is stored in CRT FIFO and subsequently displayed.
In granting access to system memory bus 173 to graphics controller 170, host controller 140 may need to resolve competing access requests for system memory bus 173 from other units such as CPU 120 or I/O device 150. Since system memory bus 173 typically permits access to only one of these units, host controller 140 needs to arbitrate that which one of these units should be allowed access when multiple requests occur at the same time.
Typical prior art host controllers give a high priority to graphics controllers in granting access to system memory bus 173 in order to meet the display data requirements of display unit 160. In one known information processing system, graphics controller 170 is given the highest priority for fetching display data from the frame buffer 130. Such a priority scheme may insure a reliable refresh rate, and hence an acceptable display quality on display unit 160.
However, such a priority system may cause performance degradation of the other units such as CPU 120 or I/O device 150, thereby resulting in the performance degradation of overall information processing system 100. For example, if CPU 120 and graphics controller 170 need access to system memory bus 173 at the same time, CPU 120 will need to wait until graphics controller 170 completes reading the display data from frame buffer 130 because of the higher priority granted to graphics controller 170. To the extent CPU 120 is forced to be idle during this wait, the throughput performance of overall information processing system 100 may be degraded.
In comparison with information processing system 10 of FIG. 1, information processing system 100 of FIG. 2 may experience a significant performance degradation due to the higher priority granted to the display data memory requests of the graphics controller. This is because access to frame buffer in FIG. 2 by graphics controller 170 is via system memory bus 173 which is shared by other units (e.g. CPU, I/O devices), whereas graphics controller 70 of FIG. 1 has a dedicated bus 78 to access frame buffer 80.
It is further well known that system memory bus 173 is idle or unused at other times. It would therefore be desirable that the graphics controller retrieve the display data during this idle time so that system memory bus 173 is available for other units when these units so require. This will ensure that the throughput performance of the overall information processing system is enhanced.